Patents Examined by Andrew Caldwell

Patent number: 11023205Abstract: Negative zero control for execution of an instruction. A process obtains an instruction to perform operation(s) using an input value. The instruction includes a negative zero control indicator indicating whether negative zero control is enabled for execution of the instruction. The process executes the instruction, the executing including performing the operation(s) using the input value to obtain a result having a sign, determining whether to control the sign of the result, the determining being based at least in part on the negative zero control indicator being set to a defined value, and performing further processing, as part the executing the instruction, based on the determining.Type: GrantFiled: February 15, 2019Date of Patent: June 1, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cedric Lichtenau, Reid Copeland, Petra Leber, Silvia M. Mueller, Jonathan D. Bradbury, Xin Guo

Patent number: 11023209Abstract: An electric device for a hardware random number generator is provided. The hardware random number generator comprises: one or more bitcells which comprise a first pair of a first transistor and a first tunable resistor and a second pair of a second transistor and a second tunable resistor, with the first pair is crosscoupled with the second pair.Type: GrantFiled: January 25, 2019Date of Patent: June 1, 2021Assignee: International Business Machines CorporationInventor: Kangguo Cheng

Patent number: 11023208Abstract: A true random number generator includes a latch circuit, a noise circuit coupled to the latch circuit and an equalization circuit coupled to the inputs of the latch circuit, the equalization circuit being configured to maintain the latch circuit in a balanced state and to allow the latch circuit to resolve from a metastable state based on a timing control. A method of generating a random number output includes maintaining a latch circuit in a balanced state by turning on an equalization circuit coupled to the inputs of the latch circuit, coupling at least one noise source to the latch circuit, allowing the latch circuit to resolve from a metastable state by turning off the equalization circuit and repeatedly turning the equalization circuit on and off based on a timing control.Type: GrantFiled: January 23, 2019Date of Patent: June 1, 2021Assignee: International Business Machines CorporationInventors: Chitra K. Subramanian, Ghavam G. Shahidi

Patent number: 11016731Abstract: Disclosed embodiments relate to performing floatingpoint (FP) arithmetic. In one example, a processor is to decode an instruction specifying locations of first, second, and third floatingpoint (FP) operands and an opcode calling for accumulating a FP product of the first and second FP operands with the third FP operand, and execution circuitry to, in a first cycle, generate the FP product having a FuzzyJbit format comprising a sign bit, a 9bit exponent, and a 25bit mantissa having two possible positions for a JBit and, in a second cycle, to accumulate the FP product with the third FP operand, while concurrently, based on Jbit positions of the FP product and the third FP operand, determining an exponent adjustment and a mantissa shift control of a result of the accumulation, wherein performing the exponent adjustment concurrently enhances an ability to perform the accumulation in one cycle.Type: GrantFiled: March 29, 2019Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Amit Gradstein, Simon Rubanovich, Zeev Sperber

Patent number: 11018692Abstract: Computerimplemented methods, systems, and devices to perform lossless compression of floating point format timeseries data are disclosed. A first data value may be obtained in floating point format representative of an initial timeseries parameter. For example, an output checkpoint of a computer simulation of a realworld event such as weather prediction or nuclear reaction simulation. A first predicted value may be determined representing the parameter at a first checkpoint time. A second data value may be obtained from the simulation. A prediction error may be calculated. Another predicted value may be generated for a next point in time and may be adjusted by the previously determined prediction error (e.g., to increase accuracy of the subsequent prediction). When a third data value is obtained, the adjusted prediction value may be used to generate a difference (e.g., XOR) for storing in a compressed data store to represent the third data value.Type: GrantFiled: July 29, 2020Date of Patent: May 25, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Anirban Nag, Naveen Muralimanohar, Paolo Faraboschi

Patent number: 11010662Abstract: Massively parallel neural inference computing elements are provided. A plurality of multipliers is arranged in a plurality of equalsized groups. Each of the plurality of multipliers is adapted to, in parallel, apply a weight to an input activation to generate an output. A plurality of adders is operatively coupled to one of the groups of multipliers. Each of the plurality of adders is adapted to, in parallel, add the outputs of the multipliers within its associated group to generate a partial sum. A plurality of function blocks is operatively coupled to one of the plurality of adders. Each of the plurality of function blocks is adapted to, in parallel, apply a function to the partial sum of its associated adder to generate an output value.Type: GrantFiled: March 4, 2020Date of Patent: May 18, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Steven K. Esser, Myron D. Flickner, Jennifer Klamo, Dharmendra S. Modha, Hartmut Penner, Jun Sawada, Brian Taba

Patent number: 11010635Abstract: A method for processing electronic data includes the steps of transforming the electronic data to a matrix representation including a plurality of matrices; decomposing the matrix representation into a series of matrix approximations; and processing, with an approximation process, the plurality of matrices thereby obtaining a lowrank approximation of the plurality of matrices.Type: GrantFiled: September 10, 2018Date of Patent: May 18, 2021Assignee: City University of Hong KongInventors: Hing Cheung So, WenJun Zeng, Jiayi Chen, Abdelhak M. Zoubir

Patent number: 11010131Abstract: An integrated circuit may include a floatingpoint adder. The adder may be implemented using a dualpath adder architecture having a near path and a far path. The near path may include a leading zero anticipator (LZA), a comparison circuit for comparing an exponent value to an LZA count, and associated circuitry for handling subnormal numbers. The far path may include a subtraction circuit for computing the difference between a received exponent value and a minimum exponent value, at least two shifters for shifting far greater and far lesser mantissa values in parallel, and associated circuitry for handling subnormal numbers. The adder may be dynamically configured to support a first mode that processes FP16 at inputs and outputs, a second mode that processes modified FP16? inputs, and a third mode that processes FP16? at inputs and outputs.Type: GrantFiled: September 14, 2017Date of Patent: May 18, 2021Assignee: Intel CorporationInventors: Martin Langhammer, Bogdan Pasca

Patent number: 11003985Abstract: Provided is a convolutional neural network system including a data selector configured to output an input value corresponding to a position of a sparse weight from among input values of input data on a basis of a sparse index indicating the position of a nonzero value in a sparse weight kernel, and a multiplyaccumulate (MAC) computator configured to perform a convolution computation on the input value output from the data selector by using the sparse weight kernel.Type: GrantFiled: November 7, 2017Date of Patent: May 11, 2021Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jin Kyu Kim, Byung Jo Kim, Seong Min Kim, JuYeob Kim, Mi Young Lee, Joo Hyun Lee

Patent number: 10997277Abstract: An integrated circuit device such as a neural network accelerator can be programmed to select a numerical value based on a multinomial distribution. In various examples, the integrated circuit device can include an execution engine that includes multiple separate execution units. The multiple execution units can operate in parallel on different streams of data. For example, to make a selection based on a multinomial distribution, the execution units can be configured to perform cumulative sums on sets of numerical values, where the numerical values represent probabilities. In this example, to then obtain cumulative sums across the sets of numerical values, the largest values from the sets can be accumulated, and then added, in parallel to the sets. The resulting cumulative sum across all the numerical values can then be used to randomly select a specific index, which can provide a particular numerical value as the selected value.Type: GrantFiled: March 26, 2019Date of Patent: May 4, 2021Assignee: Amazon Technologies, Inc.Inventors: Yu Zhou, Vignesh Vivekraja, Ron Diamant

Patent number: 10997275Abstract: A method for an associative memory array includes storing each column of a matrix in an associated column of the associative memory array, where each bit in row j of the matrix is stored in row Rmatrixrowj of the array, storing a vector in each associated column, where a bit j from the vector is stored in an Rvectorbitj row of the array. The method includes simultaneously activating a vectormatrix pair of rows Rvectorbitj and Rmatrixrowj to concurrently receive a result of a Boolean function on all associated columns, using the results to calculate a product between the vectormatrix pair of rows, and writing the product to an Rproductj row in the array.Type: GrantFiled: March 23, 2017Date of Patent: May 4, 2021Assignee: GSI Technology Inc.Inventors: Avidan Akerib, Pat Lasserre

Patent number: 10990355Abstract: The present innovative solution solves the problem of generating pseudorandom numbers that have practically infinite period, while requiring limited processing resources and operating significantly faster that known pseudorandom number generators. A sequence of pseudorandom numbers is created by a linear congruential generator using a large seed number and the sequence is used to create a big number. The big number is formed by raising each of at least two pseudorandom numbers and their sum to the same power. The big number is then selectively split into a sequence of aperiodic pseudorandom numbers which are output for use in any suitable application and for seeding the present generator.Type: GrantFiled: July 10, 2020Date of Patent: April 27, 2021Inventor: Panagiotis Andreadakis

Patent number: 10984074Abstract: Disclosed embodiments relate to an accelerator for sparsedense matrix instructions. In one example, a processor to execute a sparsedense matrix multiplication instruction, includes fetch circuitry to fetch the sparsedense matrix multiplication instruction having fields to specify an opcode, a dense output matrix, a dense source matrix, and a sparse source matrix having a sparsity of nonzero elements, the sparsity being less than one, decode circuitry to decode the fetched sparsedense matrix multiplication instruction, execution circuitry to execute the decoded sparsedense matrix multiplication instruction to, for each nonzero element at row M and column K of the specified sparse source matrix generate a product of the nonzero element and each corresponding dense element at row K and column N of the specified dense source matrix, and generate an accumulated sum of each generated product and a previous value of a corresponding output element at row M and column N of the specified dense output matrix.Type: GrantFiled: February 24, 2020Date of Patent: April 20, 2021Assignee: Intel CorporationInventors: Srinivasan Narayanamoorthy, Nadathur Rajagopalan Satish, Alexey Suprun, Kenneth J. Janik

Patent number: 10983756Abstract: In an aspect, a processor includes circuitry for iterative refinement approaches, e.g., NewtonRaphson, to evaluating functions, such as square root, reciprocal, and for division. The circuitry includes circuitry for producing an initial approximation; which can include a LookUp Table (LUT). LUT may produce an output that (with implementationdependent processing) forms an initial approximation of a value, with a number of bits of precision. A limitedprecision multiplier multiplies that initial approximation with another value; an output of the limited precision multiplier goes to a full precision multiplier circuit that performs remaining multiplications required for iteration(s) in the particular refinement process being implemented. For example, in division, the output being calculated is for a reciprocal of the divisor.Type: GrantFiled: October 17, 2014Date of Patent: April 20, 2021Assignee: Imagination Technologies LimitedInventor: Leonard Rarick

Patent number: 10977339Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.Type: GrantFiled: November 14, 2019Date of Patent: April 13, 2021Assignee: Mythic, Inc.Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, PeiCi Wu, Andrew Morten

Patent number: 10970201Abstract: A system, apparatus and method for utilizing a transpose function to generate a twodimensional array from threedimensional input data. The use of the transpose function reduces redundant elements in the resultant twodimensional array thereby increasing efficiency and decreasing power consumption.Type: GrantFiled: October 24, 2018Date of Patent: April 6, 2021Assignee: Arm LimitedInventor: Paul Nicholas Whatmough

Patent number: 10963220Abstract: An N×N multiplier may include a N/2×N first multiplier, a N/2×N/2 second multiplier, and a N/2×N/2 third multiplier. The N×N multiplier receives two operands to multiply. The first, second and/or third multipliers are selectively disabled if an operand equals zero or has a small value. If the operands are both less than 2N/2, the second or the third multiplier are used to multiply the operands. If one operand is less than 2N/2 and the other operand is equal to or greater than 2N/2, the first multiplier is used or the second and third multipliers are used to multiply the operands. If both operands are equal to or greater than 2N/2, the first, second and third multipliers are used to multiply the operands.Type: GrantFiled: February 14, 2019Date of Patent: March 30, 2021Inventors: Ilia Ovsiannikov, Ali Shafiee Ardestani, Joseph Hassoun, Lei Wang

Patent number: 10956536Abstract: A processing device is provided which comprises memory configured to store data and a plurality of processor cores in communication with each other via first and second hierarchical communication links. Processor cores of a first hierarchical processor core group are in communication with each other via the first hierarchical communication links and are configured to store, in the memory, a subportion of data of a first matrix and a subportion of data of a second matrix. The processor cores are also configured to determine a product of the subportion of data of the first matrix and the subportion of data of the second matrix, receive, from another processor core, another subportion of data of the second matrix and determine a product of the subportion of data of the first matrix and the other subportion of data of the second matrix.Type: GrantFiled: October 31, 2018Date of Patent: March 23, 2021Assignee: Advanced Micro Devices, Inc.Inventors: Shaizeen Aga, Nuwan Jayasena, Allen H. Rush, Michael Ignatowski

Patent number: 10949495Abstract: A device configured to emulate a correlithm object system includes a memory that stores a node table. The node table identifies a plurality of source correlithm objects and a corresponding plurality of target correlithm objects. A node receives a first input correlithm object associated with a first timestamp, computes distances between the first input correlithm object and each of the source correlithm objects in the node table, and identifies a first source correlithm object from the node table with the shortest distance. The node identifies a first target correlithm object from the node table linked with the identified first source correlithm object, and outputs the first target correlithm object. The memory stores a node output table that identifies the first target correlithm object associated with the first source correlithm object, the first timestamp, and the computed distance between the first input correlithm object and the first source correlithm object.Type: GrantFiled: March 11, 2019Date of Patent: March 16, 2021Assignee: Bank of America CorporationInventor: Patrick N. Lawrence

Patent number: 10949494Abstract: A correlithm object processing system uses one or more mobile correlithm object devices to emulate the functionality of one or more of sensors, nodes, and actors. The mobile correlithm object devices may be deployed to different parts of a system or network to perform particular tasks. The mobile correlithm object devices may periodically communicate with one another or with other elements of the correlithm object processing system.Type: GrantFiled: March 11, 2019Date of Patent: March 16, 2021Assignee: Bank of America CorporationInventor: Patrick N. Lawrence